This invention relates to a semiconductor memory device with a sense amplifier.
In a semiconductor memory device, whether or not the data is reliably stored in each memory cell is an important matter. In the semiconductor memory device of the type in which transistors with floating gates are used for the memory cells, data of logical "1" is expressed in terms of a charged state of the memory cell Specific ambient conditions, structural defects of the memory cell, etc. can often cause the discharge of stored electrons from the memory cell. Therefore, it is necessary to frequently check the charged or stored state of the cells, which determines the reliability of the stored data. The reliability of the stored data can also be described by the stability of the threshold voltage of the cell transistor. After a memory device is placed at a high temperature for a long period of time, if the threshold voltage of the cell transistors does not change, the stored data is reliable. In this respect, the reliability of the stored data can be known by checking the threshold values of the cell transistors.
FIG. 1 shows a conventional memory device provided with sense amplifier 20 for detecting data stored in cell transistor 11. Transistor 11 is of the type having a control gate Gc and a floating gate Gf. By injecting charges into the floating gate, data of "1" is stored in the cel. By discharging the cell, data of "0" is stored in the cell. If charges are injected into the discharged memory cell, the threshold value Vth of the cell changes from that in the discharged state. The first end of the source-drain path of cell transistor 11 is grounded. The second end of the path is connected to load circuit 12 with a voltage level changing function. Load circuit 12 is comprised of a couple of N channel MOS transistors 102 and 104, a couple of inverters 106 and 108, N channel MOS transistor 110, and N channel MOS transistor 112. Each of transistors 102 and 104 is connected with its source-drain path connected, at one end, to power source potential Vc, and, at the other end, to the second end of cell transistor 11 by input port Tin 12 of load circuit 12. Inverters 106 and 108 are connected between the second end of cell transistor 11 and the gates of transistors 102 and 104. The inverters each invert the logical level of the data from cell 11. Transistor 110 is connected with its drain-source path inserted between the second end of cell transistor 11 and output port Tout12 of load circuit 12, and with its gate connected to receive the output signal from inverter 108. One end of the drain-source path of MOS transistor 112 and its gate are connected together to power source voltage Vcc. The other end of the drain-source path is connected to the output port Tout12 of load circuit 12.
A dummy cell is further provided in this memory device. Transistor 13 constitutes the dummy cell, also having a double layered gate structure including floating gate Gf and control gate Gc. The dummy cell is not charged, with its threshold voltage set at its initial value. The drain-source of the transistor 13 is connected, at one end, to ground, while, at the other end, to the input port Tin14 of another load circuit 14 with a voltage level changing function. The circuit arrangement of this load circuit 14 is substantially equivalent to that of load circuit 12. This circuit 14 will be described, using the same reference numerals designating the same portions as those of load circuit 12.
Load circuit 14 is comprised of a couple of N channel MOS transistors 102 and 104, a couple of inverters 106 and 108, N channel MOS transistor 110, and N channel MOS transistor 112. Each of transistors 102 and 104 is connected so that its source-drain path is connected at one end to power source potential Vc, and at the other end to the second end of dummy cell transistor 13 through input port Tin14 of load circuit 14. Inverters 106 and 108 are connected between the second end of dummy cell transistor 13 and the gates of transistors 102 and 104. The inverters each invert the logical level of the data from cell 13. Transistor 110 is connected with its drain-source path inserted between the second end of cell transistor 13 and output port Tout14 of load circuit 14, and with its gate connected to receive the output signal from inverter 108. One end of the drain-source path of MOS transistor 112 and its gate are connected together to power source voltage Vc. The other end of the drain-source path is connected to the output port Tout14 of load circuit 14.
A voltage at the output Tout12 of circuit 12 is used for a voltage Vmem representing the data stored in the memory cell 11. A voltage at the output Tout14 of circuit 14 is used as a reference voltage Vref. The voltages are applied to sense amplifier 20. More specifically, they are applied to the gates of N channel MOS transistors 21 and 22 constituting the input circuit 23 of amplifier 20.
Sense amplifier 20 further comprises current mirror circuit 26, N channel MOS transistor 27, control signal generation circuit 28, and inverter 29. In input circuit 23, transistor 21 receives at its gate the output voltage of load circuit 12. Transistor 22 receives at its gate the output voltage of load circuit 14. Current mirror circuit 26 is made up of a pair of P channel transistors 24 and 25, which form a load circuit for input circuit 23. Transistor 27 renders input circuit 23 inactive during the inactive period of chip enable signal CE. The circuit 28 generates a control signal for controlling transistor 27 in response to chip enable signal CE. The sources of transistors 21 and 22 are both interconnected and grounded through the drainsource path of transistor 27. The drains of transistors 21 and 22 are both connected to power source potential Vc by the drain-source paths of transistors 24 and 25. The gate and drain of transistor 25 are interconnected. An interjunction between transistors 21 and 24 is connected to the input terminal of inverter 29. The data detected by sense amplifier 20 is supplied from this inverter 29.
Control signal generation circuit 28 comprises P channel MOS transistor 202, N channel MOS transistors 204 and 206 which are connected in series between potential Vc and ground GND, and N channel MOS transistor 208 coupled across transistor 206. Chip enable signal CE is connected to the gates of transistors 202 and 208. The gate and drain of transistor 204 are connected with each other, as is also the case for transistor 206. The drains of transistors 206 and 208 are both connected to the gate of transistor 27.
Bias circuit 30 is connected to the gate of dummy cell 13. Circuit 30 is made up of depletion type MOS transistor 31, and enhancement type MOS transistors 32 to 34. These transistors are connected in series between potential Vc and ground GND. When test signal T input to the gate of transistor 34 is at logical "1" level, bias circuit 30 provides a predetermined bias potential. The gates of transistors 31 and 32 are interconnected and further connected to a series connection point of transistors 31 and 32. This connection point is connected to the gate of transistor 13. Transistor 33 is connected i a diode fashion. A drive signal is supplied from a decoder (not shown) to the gate of memory cell 11.
The reliability of the stored data of cell 11, that is, the storage of charges in this cell, is ensured in the following way. Test signal T is set at "1" level. Thus, transistor 34 in bias circuit 30 is turned on. Therefore, applied to the gate Gc of dummy cell 13 is a bias voltage corresponding to the sum of the threshold voltages of transistors 32 and 33. At the same time, a "1" level voltage is applied to the gate Gc of the control gate of cell 11 by way of a decoder (not shown).
The power source voltage Vc is then progressively increased above the threshold voltage of cell 11. During this increase of voltage Vc, cell transistor 11 is turned on at an increated value of voltage Vc.
The threshold voltages VthC (memory cell 11), VthD(dummy cell 13), Vth32 and Vth33 of transistors 11, 13, 32 and 33 respectively, and power source potential Vc are related by the following relation (1). EQU Vc-VthC&gt;Vth32+Vth33-VthD . . . . (1)
When formula (1) holds, cell transistor 11 is turned on and the voltage corresponding to the data stored in cell 1 (the output voltage of load circuit 12) is smaller than reference voltage Vref, or the output voltage of load circuit 14. That is to say, when formula (1) holds, the data detected by sense amplifier 20 is inverted in level. The voltage Vc at this level inversion is expressed by Vc1.
Then, the memory device is subjected to a high temperature of 150.degree. C. for a long time. Then, the above measurement of the device is again performed. In the measurement, potential Vc at the level insertion of the detected data is expressed by Vc2. A state that the potentials Vc1 and Vc2 are equal or substantially equal indicates that the reliability of the stored data of cell 11 is good. Value Vc2 smaller than Vcl by a given value or more implies that floating gate Gf of cell 11 has been discharged. When this occurs, the reliability is low.
In a ROM of the type in which data is electrically written and erased by ultraviolet rays, the threshold voltage of the cell varies within a positive polarity region. Therefore, the above measurements are applicable to the reliability measurement of the ROM. In an EEPROM in which data write and erasure are both electrically made, when the cell is discharged by applying to high potential to the drain of the cell, the floating gate of the cell is positively charged, and hence the threshold voltage varies in the negative polarity region. The above measuring method is not applicable to the EEPROM. This is because if potential Vc is decreased within the positive polarity domain, the dummy cell is not turned off, and is kept in an on state. To turn off cell 11, potential Vc must be placed in the negative polarity region for the circuit to be operable. For this reason, the above measurement of the cell reliability is not available for a cell with the threshold voltage of negative polarity.